Factory Price Olt Epon - 1000BASE-PX20++ EPON OLT SFP Transceiver ZL5432099-ICS – HDV

Product Applications
GEPON OLT For P2MP Application
General
The HDV ZL5432099-ICS transceiver with supports data rate of typical 1.25 Gbps for GEPON OLT application up to 20km transmission distance, it’s designed meeting with China Telecom EPON equipment technical requirement V2.1 1000BASE-PX20+ specifications. SC rececptacle is for optical interface.

The module provides digital diagnostic information of its operating conditions and status, including transmitting power, laser bias, receiver input optical power, module temperature, and supply voltage.  Calibration and alarm/warning threshold data are written and stored in internal memory (EEPROM).  The memory map is compatible with SFF-8472, as shown in Fig. 2. The diagnostic data are raw A/D values and must be converted to real world units using calibration constants stored in EEPROM locations 56 – 95 in A2h.

Fig 2 EEPROM Information
Performance Specifications

Note:
1. Minimum Sensitivity and saturation levels for an 8B10B 2⁷-1 PRBS. BER≤10^-12, 1.25Gpbs, ER=9dB

EEPROM Information

EEPROM Serial ID Memory Contents (A0h)

 Alarm and Warning Thresholds (Serial ID A2H)

Digital Diagnostic Monitor Accuracy

 PIN Diagram

PIN Description

Notes:

1. TX Fault is an open collector/drain output, which should be pulled up with a 4.7K–10KΩ resistor on the host board. Pull up voltage between 2.0V and VccT, R+0.3V. When high, output indicates a laser fault of some kind. Low indicates normal operation. In the low state, the output will be pulled to < 0.8V.
2. TX disable is an input that is used to shut down the transmitter optical output.  It is pulled up within the module with a 4.7–10 KΩ resistor.  Its states are:

Low (0 – 0.8V):   Transmitter on
(>0.8, < 2.0V):   Undefined
High (2.0 – 3.465V): Transmitter Disabled
Open:       Transmitter Disabled

1. Mod-Def 0,1,2. These are the module definition pins. They should be pulled up with a 4.7K – 10KΩ resistor on the host board. The pull-up voltage shall be VccT or VccR.

Mod-Def 0 is grounded by the module to indicate that the module is present
Mod-Def 1 is the clock line of two wire serial interface for serial ID
Mod-Def 2 is the data line of two wire serial interface for serial ID
4.  LOS (Loss of Signal) is an open collector/drain output, which should be pulled up with a 4.7K – 10KΩ resistor. Pull up voltage between 2.0V and VccT, R+0.3V. When high, this output indicates the received optical power is below the worst-case receiver sensitivity (as defined by the standard in use). Low indicates normal operation. In the low state, the output will be pulled to < 0.8V.

1. VeeR and VeeT may be internally connected within the SFP module.
2. RD-/+: These are the differential receiver outputs. They are DC coupled 100Ω differential lines which should be terminated with 100Ω (differential) at the user SERDES.
3. VccR and VccT are the receiver and transmitter power supplies. They are defined as 3.3V ±5% at the SFP connector pin. Maximum supply current is 450mA. Recommended host board power supply filtering is shown below. Inductors with DC resistance of less than 1Ω should be used in order to maintain the required voltage at the SFP input pin with 3.3V supply voltage.  When the recommended supply filtering network is used, hot plugging of the SFP transceiver module will result in an inrush current of no more than 30 mA greater than the steady state value.  VccR and VccT may be internally connected within the SFP transceiver module.
4. TD-/+: These are the differential transmitter inputs. They are AC-coupled, differential lines with 100Ω differential termination inside the module. The AC coupling is done inside the module and is thus not required on the host board.

Package Diagram

Recommended Circuit

 
Note:
Tx：AC coupled internally. 
R1=R2=150Ω.
Rx： LVPECL output, DC coupled internally.
Input stage in SerDes IC with internal bias to Vcc-1.3V
R3=R4=R5=R6=N.C
Input stage in SerDes IC without internal bias to Vcc-1.3V
R3=R4=130Ω, R5=R6=82Ω.
Timing Parameter Definition


Timing Of Digital RSSI

 Change History