ADI ADIN2111 Ethernet switch will be the main introduction object of the following content. Through this article, the editor hopes that everyone can have some knowledge and understanding of its related situation and information. The details are as follows.
The ADIN2111 is a low power, low complexity, dual Ethernet port switch that integrates a 10BASE-T1L PHY and a Serial Peripheral Interface (SPI) port. The device uses a low power constrained node for Industrial Ethernet applications and is compliant with the IEEE® 802.3cg-2019™ Ethernet standard for long distance 10 Mbps Single Pair Ethernet (SPE). The switch (cut-through or store-and-forward) supports multiple cabling configurations between the two Ethernet ports and the SPI host port, providing a flexible solution for line, daisy-chain or ring network topologies.
The ADIN2111 supports up to 1700 meters of cable reach with ultra-low power consumption of 77 mW. The two PHY cores support 1.0 V p-p and 2.4 V p-p operation as defined in the IEEE 802.3cg standard and can be powered from a single 1.8 V or 3.3 V supply rail. The ADIN2111 is available in an unmanaged configuration where the device automatically forwards traffic between two Ethernet ports.
The device integrates a switch, two Ethernet physical layer (PHY) cores with media access control (MAC) interfaces, and all associated analog circuitry, input and output clock buffering devices. The device also includes internal buffer queues, SPI and subsystem registers, and control logic to manage reset and clock control and hardware pin configuration.
The ADIN2111 integrates voltage supply monitoring circuitry and power-on-reset (POR) circuitry for improved system-level robustness. The 4-wire SPI used to communicate with the host can be configured as OPEN Alliance SPI or Generic SPI. Both modes support optional data protection or Cyclic Redundancy Check (CRC).
Each PHY of the ADIN2111 can also be configured to generate a hardware interrupt after a hardware reset (RESET pin pulled low) by setting the CRSM_HRD_RST_IRQ_EN bit in the corresponding PHY’s System Interrupt Mask Register (CRSM_IRQ_MASK). Although both PHYs can be used to generate hardware interrupts, PHY 1 is recommended for this purpose. After the SPI master receives a hardware interrupt from the INT pin, the PHYINT bit (respectively, the P2_PHYINT bit) on status register 0 (respectively, status register 1) is also set to 1, notifying the interrupt from PHY 1 (respectively, PHY 2) . The source of the interrupt can then be checked using the CRSM_HRD_RST_IRQ_LH bit in the corresponding PHY’s System Interrupt Status Register (CRSM_IRQ_STATUS).
For system verification using an external host controller, each PHY of the ADIN2111 can be requested to generate a hardware interrupt on the INT pin using the CRSM_SW_IRQ_REQ bit in the System Interrupt Mask Register (CRSM_IRQ_MASK). Although both PHYs can be used to generate hardware interrupts, PHY 1 is recommended for this purpose. After the SPI master receives a hardware interrupt from the INT pin, the PHYINT bit (respectively, the P2_PHYINT bit) in status register 0 (respectively, status register 1) is also set to 1, notifying the interrupt from PHY 1 (respectively, PHY 2) . The source of the interrupt can then be checked using the CRSM_SW_IRQ_LH bit in the corresponding PHY’s System Interrupt Status Register (CRSM_IRQ_STATUS).
Each ADIN2111 PHY can also generate a system error interrupt. The interrupt flags are located in the reserved bits section of the corresponding PHY’s System Interrupt Status Register (CRSM_IRQ_STATUS). The system interrupt mask register (CRSM_IRQ_MASK) must be configured on the corresponding PHY to enable system error interrupts. See Table 212 for details on interrupt masking. The ADIN2111 must undergo a hardware reset to recover from a system error interrupt from one of the two PHYs (the CRSM_IRQ_STATUS reserved bit reads 1 on the respective PHY).
The ADIN2111 includes a power supply monitoring circuit to ensure that the chip has the proper voltage supply before initiating the power-up sequence. During power-up, the ADIN2111 remains in a hardware reset state until each supply exceeds its minimum rising threshold and the supply is considered good.
A hardware reset is initiated by the power-on reset circuit or by driving the RESET pin low for at least 10 µs. The ADIN2111 includes a deglitch circuit on this pin to reject pulses shorter than 1 µs. When the RESET pin is deasserted, all input/output (I/O) pins remain in tri-state mode, the hardware configuration pins are latched, and the I/O pins are configured to their functional mode. The crystal oscillator circuit is enabled when all external and internal power supplies are valid and stable. After the crystal starts and stabilizes, the phase-locked loop (PLL) is enabled. After a delay of 90 ms (max) after the RESET pin is deasserted, all internal clocks are asserted, the internal logic is released from reset, and all internal SPI, PHY 1 and PHY 2 registers are accessible from the SPI. The CLK25_REF clock output is held low when the RESET pin is taken low and remains low for 70 ms (max) after the RESET pin is taken low.
All the above content is all the introduction brought by the editor this time. If you want to know more about it, you may wish to explore it on our website or on Baidu and Google.
https://www.smart-xlink.com/products.html
Web: www.hdv-tech.com <https://hdv-tech.en.alibaba.com >
Google Website:https://www.hdv-fiber.com/
HDV Factory Link:https://youtu.be/xpIZK8Zm4Og