Notes:
Low (0 – 0.8V): Transmitter on
(>0.8, < 2.0V): Undefined
High (2.0 – 3.465V): Transmitter Disabled
Open: Transmitter Disabled
Mod-Def 0 is grounded by the module to indicate that the module is present
Mod-Def 1 is the clock line of two wire serial interface for serial ID
Mod-Def 2 is the data line of two wire serial interface for serial ID
4. LOS (Loss of Signal) is an open collector/drain output, which should be pulled up with a 4.7K – 10KΩ resistor. Pull up voltage between 2.0V and VccT, R+0.3V. When high, this output indicates the received optical power is below the worst-case receiver sensitivity (as defined by the standard in use). Low indicates normal operation. In the low state, the output will be pulled to < 0.8V.
Package Diagram
Recommended Circuit
Note:
Tx:AC coupled internally.
R1=R2=150Ω.
Rx: LVPECL output, DC coupled internally.
Input stage in SerDes IC with internal bias to Vcc-1.3V
R3=R4=R5=R6=N.C
Input stage in SerDes IC without internal bias to Vcc-1.3V
R3=R4=130Ω, R5=R6=82Ω.
Timing Parameter Definition
Timing Of Digital RSSI
PARAMETER |
SYMBOL |
MIN |
TYP |
MAX |
UNITS |
Packet Length |
- |
600 |
- |
- |
ns |
Trigger delay |
Td |
100 |
- |
- |
ns |
RSSI Trigger and Sample Time |
Tw |
500 |
- |
- |
ns |
Internal delay |
Ts |
500 |
- |
- |
us |
Change History
Version |
Change Description |
Issued By |
Checked By |
Appoved By |
Release Date |
A |
Initial release |
2016-01-18 |
REV: | A |
DATE: | August 30,2012 |
Write by: | HDV phoelectron technology LTD |
Contact: | Room703,Nanshan district science college town, Shenzhen, China |
WEB: | Http://www.hdv-tech.com |